Digital-analog (D/A) converters are widely used in many applications, such as wireless communications, signal reconstruction, waveforms generation etc. Basically, a D/A converter may be realized with an array of conducting branches that generate binary weighted constant currents (binary array) and/or identical currents (unary array). These conducting branches may include capacitors or current generators, selectable by respective switches for delivering current toward a summing line or toward ground.
For sake of simplicity, let us refer to a D/A converter, the conducting branches of which are realized with current generators, though what will be said will hold, mutatis mutandis, also for conducting branches realized with switched capacitors.
The conducting branches of a binary array are selected by respective bits of an input bit string, while the conducting branches of an unary array are selected according to a fixed switching sequence for making the unary array generate a total current corresponding to the input digital value.
For better comprehending the field of utility of an embodiment of this invention, let us refer to the so-called segmented converters, which generally have a binary weighted array of conducting branches, selected by the least significant bits of an input digital string, and an unary array that delivers a current corresponding, to the digital value represented by the most significant bits, that is according to a so-called thermometer or thermometric decoding.
A sample unary array is depicted in FIG. 1. As may be noticed, the current generators are selected according to a certain switching sequence and the output current lout corresponds to the sum of the currents circulating in the selected branches. Optionally, there may be a “dummy” area in the unary array, which may be used for realizing biasing circuits. In segmented digital-to-analog converters, the “dummy” area may be used for realizing a binary array.
When the digital input value to be converted by the unary array represents a certain number n, the current generators of the unary array from 1 to n are switched on, thus generating an output current lout proportional to the digital input number n.
Ideally, a D/A converter should generate an output signal that varies linearly with the input bit string, which would happen if all the conducting branches were identical. Unfortunately, mismatches between conducting branches due to inaccuracies of the fabrication process (process spread), make the current delivered by each branch not exactly equal to the design value, but affected by an error that may depend on the position of the conducting branch on the silicon substrate.
In general, unary arrays are affected by a differential non-linearity (INL) error and by an integral non-linearity (INL) error.
Indicating with Ī the average current delivered by the branches of an unary array and with Ij the current delivered by the j-th branch of the array in the switching sequence,Ij=Ī·(1+εj) wherein εj is the relative deviation of the current Ij from the average current Ī.
In an unary array not having a dummy area, the DNL error of the k-th branch in the switching sequence isDNL(k)=εk which represents a non-uniform deviation in the ideal current step amplitude between adjacent bit strings.
The INL error function is defined as       INL    ⁡          (      k      )        =            ∑              j        =        1            k        ⁢                   ⁢          ɛ      j      and gives the deviation of the real analog output signal from its ideal value as a percentage of the average current Ī for any value “k” of the switching sequence.
The absolute INL error of a switching sequence is the maximum absolute value of the relative INL error function.
An introduction on the INL and DNL errors of an unary array of a D/A thermometrically decoded converter is carried out in the article by Y. Cong and R. L. Geiger “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays”, IEEE Trans. on circuits and systems—II: analog and digital signal processing, Vol. 47, No. 7, pages 585-595, July 2000.
The DNL error of a branch can be reduced only by reducing the process spread and is independent from the switching sequence. By contrast, the INL error function strongly depends on the switching sequence, as it may be easily inferred from the following example.
Two possible switching sequences of a mono-dimensional unary array having eight conducting branches are shown in FIG. 1A. The conducting branches are affected by the indicated DNL errors (ε). The absolute values of the underlined numbers are the absolute INL errors of the switching sequences.
As may be noticed, the INL error function of the sequential switching sequence shows a maximum deviation of the analog output from its ideal value in the middle of the sequence. This situation is inconvenient, because the digital values input to a D/A converter are more likely in the middle of the range of conversion, rather than at the two ends thereof. Therefore, it is more convenient to switch the mono-dimensional array of conducting branches of FIG. 1A according to a symmetrical sequence than according to a sequential sequence. Moreover, the absolute INL error for the symmetrical sequence is 7, while for the sequential sequence is 16.
In this very simple case, it is possible to determine by successive trials the switching sequence with the smallest absolute INL error, but for two-dimensional unary arrays of approximately one thousand conducting branches, the number of combinations is too large for determining a switching sequence with the desired INL error function by trials.
Many different methods of determining a switching sequence of a two dimensional unary array of conducting branches and a relative D/A converter have been proposed.
The patent U.S. Pat. No. 6,118,398 by G. J. Fisher et al. discloses a digital-analog converter having an unary array of current sources that are selected according to a sequence that ensures a relatively small absolute integral non-linearity error. The suggested switching sequence is substantially a mixed symmetrical sequence, in which the current sources that are in the middle of the array have median positions in the switching sequence, while current sources that are in borderline regions of the array are at the beginning or at the end of the sequence.
The patent U.S. Pat. No. 5,057,838 by K. Tsuji et al. discloses a D/A converter having a plurality of conducting branches of a two-dimensional array, wherein the switching sequence is determined in order to make the center of the current contributions delivered by the conducting branches of the array coincide with the center of the array.
The document “A 14-bit Intrinsic Accuracy Q2 Random Walk CMOS DAC” by Van der Plas, Steyaert et al., JSCC 12 Dec. 1999, discloses a method of determining the switching sequence of the switches of a D/A converter organized in matrix form, exploiting the so-called “Q2 random walk” algorithm.
The document “Switching Sequence Optimization for Gradient Error Compensation in Thermometer-Decoded DAC Arrays”, by Cong, Geiger, JSSC 7 Jul. 2000, discloses an algorithm to find the so-called “INL bounded” switching sequence for an unary array of branches organized in matrix form.
Unfortunately, the absolute INL errors of the D/A converters realized with the above techniques remain relatively large.